1. Field of the Invention
The present application relates to WLAN (Wireless Local Area Network) communication devices including a WLAN frequency synthesizer for generating a synthesizer signal and corresponding methods and integrated circuit chips, and in particular to the pre-processing of a reference clock signal provided to a fractional-N PLL (Phase-Locked Loop) unit within the frequency synthesizer.
2. Description of the Related Art
A wireless local area network is a flexible data communication system implemented as an extension to or as an alternative for a wired LAN. Using radio frequency or infrared technology, WLAN systems transmit and receive data over the air minimizing the need for wired connections. Thus, WLAN systems combine data connectivity with user mobility.
Today most WLAN systems use spread spectrum technology, a wideband radio frequency technique developed for use in reliable and secure communication systems. The spread spectrum technology is designed to trade off bandwidth efficiency for reliability, integrity and security. Two types of spread spectrum radio systems are frequently used: frequency hopping and direct sequence systems.
For generating a carrier signal suitable for the up-conversion of transmission signals and/or the down-conversion of reception signals, WLAN communication devices, i.e. transmitters, receivers and transceivers, include a frequency synthesizer. The frequency synthesizer comprises a very stable reference oscillator providing a reference clock signal and translates the frequency of the reference clock signal to the desired radio or infrared frequency. The frequency translation is usually achieved by a PLL unit which requires only a few components and is easily integrated.
FIG. 1 shows the components of a typical PLL-based frequency synthesizer. A VCO (Voltage-Controlled Oscillator) oscillator 160 outputs the carrier signal at an output frequency fOUT. The output frequency fOUT can be varied by varying a control voltage supplied to the VCO oscillator 160.
Part of the carrier signal is split and provided to a frequency divider 170. The frequency divider 170 divides the output frequency fOUT of the carrier signal by a division factor which can be selected by the controller 180. The resulting divider signal at the frequency f′OUT is provided to a comparator.
A reference oscillator 110 generates a reference clock signal at a reference frequency fREF. Also the reference clock signal is provided to the comparator.
The comparator, typically a phase detector or a PFD (Phase/Frequency Detector) detector 130, compares the divider signal with the reference clock signal and outputs an error signal that quantitatively indicates the phase difference between the two signals. The error signal is provided to a charge pump 140 that converts the error signal into either positive or negative charge pulses depending on whether the reference clock signal phase leads or lags the divider signal phase. These charge pulses are integrated by a loop filter 150 to generate the control voltage applied to the VCO oscillator 160 for moving the output frequency fOUT up or down until the phases are synchronized.
As illustrated in FIG. 1, the frequency synthesizer basically comprises the reference oscillator 110 and the PLL unit 120 comprising the PFD detector 130, the charge pump 140, the loop filter 150, the VCO oscillator 160, the frequency divider 170 and the controller 180.
The PLL unit 120 may be a fractional-N PLL unit. In a fractional-N PLL unit 120, the frequency divider 170 may be continually varied in a way that allows the average modulus to be specified with sub-integer (“fractional”) precision. The increased frequency divider resolution allows the reference frequency fREF to be significantly larger than the desired output frequency step size. However, since WLAN frequency synthesizers usually use crystal oscillators as the reference oscillator 110, reference frequencies fREF of up to 40 MHz only are available.
Even when the fractional-N PLL unit 120 is locked, the charge pump 140 still outputs small charge pulses caused, e.g., by non-ideal phase/frequency detection in the PFD detector 130. These pulses create sidebands, or spurs, in the output spectrum of the VCO oscillator 160 at offset frequencies equal to the reference frequency fREF. For sufficiently suppressing those spurs, the loop filter 150 may need to have a loop filter bandwidth narrower than, e.g., 1% of the reference frequency fREF.
However, there is a tradeoff between spurious suppression and loop dynamics in the fractional-N PLL unit 120. While a narrow loop filter bandwidth is required for spurious suppression, a wide loop filter bandwidth is needed for short settling times.
The settling time of a fractional-N PLL unit 120 is the time required for re-achieving stable operation once the desired output frequency fOUT of the carrier signal has been changed. Particularly in frequency hopping WLAN systems, it is critical to quickly re-lock the fractional-N PLL unit 120 after hopping from one output frequency fOUT to another.
As indicated above, the loop filter bandwidth is for instance limited to 1% of the reference frequency fREF for achieving sufficient spurious suppression. Since in prior art techniques, usually crystal oscillators are used for the reference oscillator 110 which provide reference frequencies of up to 40 MHz only, many conventional WLAN communication devices suffer from long settling times. This often leads to problems in achieving efficient transmission data rates.
Other conventional approaches decrease the settling time by using wider loop filter bandwidths. However, such systems generally have the disadvantage of suppressing spurious emissions only insufficiently. In consequence, the transmission quality is significantly reduced.
The tradeoff between spurious suppression and loop dynamics could be eased by using reference oscillators 110 that provide a higher reference frequency fREF. This may allow for increasing the loop filter bandwidth, i.e. decreasing the settling time, while still remaining below 1% of the reference frequency fREF, i.e. maintaining or even enhancing the spurious suppression.
There are crystal oscillators obtainable providing reference frequencies fREF superior to 40 MHz. However, such high frequency crystal oscillators are considerably more expensive than regular crystal oscillators. Thus, prior art WLAN communication devices employing high frequency crystal oscillators produce higher manufacturing costs and are therefore less competitive.
Further, high frequency crystal oscillators consume significantly more power than standard crystal oscillators. In consequence, existing WLAN communication devices based on high frequency crystal oscillators often have the disadvantage of providing only short battery lifetimes. Alternatively, conventional WLAN communication devices may include improved but expensive storage batteries. This again leads to the problem of increased product costs.
In addition, high frequency crystal oscillators are less reliable than standard crystal oscillators because of providing less frequency stability. In particular, high frequency crystal oscillators often reveal an increased frequency drift. Thus, the output frequency fOUT of a fractional-N PLL unit 120 locked to a high frequency crystal oscillator also suffers from an increased frequency instability. This results in that many prior art WLAN communication devices fail to keep the specified frequency accuracy.